SSE3

SSE3, also known by its Intel code name Prescott New Instructions or PNI, is the third iteration of the SSE instruction set for the IA-32 architecture. It is a SIMD instruction set.

Related Topics:
Intel - SSE - IA-32 - SIMD

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The earlier SIMD sets on the x86 platform, from oldest to newest, are MMX, 3DNow! (developed by AMD), SSE and SSE2.

Related Topics:
X86 - MMX - 3DNow! - SSE - SSE2

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Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. AMD introduced a subset of SSE3 in the revision E of their Athlon 64 CPUs, released in April 2005.

Related Topics:
Pentium 4 - AMD - Athlon 64

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SSE3 adds 13 new instructions to its predecessor, SSE2. The most notable addition is the capability to work horizontally in a register, as opposed to the more or less strictly vertical operation of all previous SSE instructions. More specifically, instructions to add and subtract the multiple values stored within a single register have been added. These instructions simplify the implementation of a number of DSP and 3D operations. There is also a new instruction to convert floating point values to integers without having to change the global rounding mode, thus avoiding costly pipeline stalls. Finally, the extension adds LDDQU, an alternative misaligned integer vector load that has better performance on Netburst architectures for loads that cross cacheline boundaries.

Related Topics:
DSP - 3D - Pipeline - Netburst

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Common Instructions: ADDSUBPD, ADDSUBPS, HADDPD, HADDPS, HSUBPD, HSUBPS, LDDQU, MOVDDUP, MOVSHDUP, MOVSLDUP

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Intel Instructions: FISTTP, MONITOR, MWAIT

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