Integrated circuit

An integrated circuit (IC) is a thin chip consisting of at least two interconnected semiconductor devices, mainly transistors, as well as passive components like resistors. As of 2004, typical chips are of size 1 cm2 or smaller, and contain millions of interconnected devices, but larger ones exist as well.

Manufacture

Fabrication

Main article: Semiconductor fabrication.

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The semiconductors of the periodic table of the chemical elements were identified as the most likely materials for a solid state vacuum tube by researchers like William Shockley at Bell Laboratories starting in the 1930s. Starting with copper oxide, proceeding to germanium, then silicon, the materials were systematically studied in the 1940s and 1950s. Today, silicon monocrystals are the main substrate used for integrated circuits (ICs) although some III-V compounds of the periodic table such as gallium arsenide are used for specialised applications like LEDs, lasers, and the highest-speed integrated circuits. It took decades to perfect methods of creating crystals without defects in the crystalline structure of the semiconducting material.

Related Topics:
Semiconductor - Periodic table - Chemical element - Solid state - Vacuum tube - William Shockley - Bell Laboratories - 1930 - Copper oxide - Germanium - Silicon - 1940 - 1950 - Monocrystal - Substrate - Gallium arsenide - LEDs - Lasers - Crystal - Crystalline structure

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Semiconductor ICs are fabricated in a layer process which includes these key process steps: -

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• Imaging
• Deposition
• Etching

The main process steps are supplemented by doping, cleaning and planarisation steps.

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A mono-crystal silicon wafer (or for special applications, silicon on sapphire or gallium arsenide wafers) are used as the substrate. Photolithography is used to mark different areas of the substrate to be doped or to have polysilicon, insulators or metal (typically aluminum) tracks deposited on them.

Related Topics:
Silicon - Wafer - Silicon on sapphire - Gallium arsenide - Photolithography - Doped - Aluminum

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• For a CMOS process, for example, a transistor is formed by the criss-crossing intersection of striped layers. The stripes can be monocrystalline substrate, doped layers, perhaps insulator layers or polysilicon layers. Some etched vias to the doped layers might interconnect layers with metal conducting tracks.
• The criss-crossed checkerboard-like (see image above) transistors are the most common part of the circuit, each checker forming a transistor.
• Resistive structures, meandering stripes of varying lengths, form the loads on the circuit. The ratio of the length of the resistive structure to its width, combined with its sheet resistivity determines the resistance.
• Capacitive structures, in form very much like the parallel conducting plates of a traditional electrical capacitor, are formed according to the area of the "plates", with insulating material between the plates. Owing to limitations in size, only very small capacitances can be created on an IC.
• More rarely, inductive structures can be simulated by gyrators.

Since a CMOS device only draws current on the transition between logic states, CMOS devices consume much less current than a bipolar device.

Related Topics:
Logic - State - Bipolar

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A memory device is the most regular type of integrated circuit; the highest density devices are thus memories; but even a microprocessor will have memory on the chip. (See the regular array structure at the bottom of the first image.) Although the structures are intricate with widths which have been shrinking for decades, the layers remain much thinner than the device widths. The layers of material are fabricated much like a photographic process, although light waves in the visible spectrum cannot be used to "expose" a layer of material as they be would too large for the features. Thus photons of higher frequencies (typically ultraviolet) are used to create the patterns for each layer. Since each feature is so small, Electron microscopes are an essential tool for a process engineer who might be debugging a fabrication process.

Related Topics:
Memory device - Microprocessor - Light - Wave - Visible spectrum - Photon - Ultraviolet - Electron microscope - Process - Engineer - Debugging

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Each device is tested before packaging. The wafer is then cut into small rectangles called dice. Each die is then connected into a package using aluminum (or occasionally gold) wires which are welded to pads, usually found around the edge of the die. After packaging, the devices go through final test on very expensive automated testers, which account for over 25 percent of the cost of fabrication. As of 2005 a fabrication facility, commonly known as a semiconductor fab, costs over a billion US Dollars to construct, because much of the operation is automated. The most advanced processes employ the following techniques:

Related Topics:
Gold - Welded - 2005 - Semiconductor

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• The wafers exceed 30 centimeters in diameter (wider than a common dinner plate).
• Use of 90 nanometer or smaller chip manufacturing process. Both Intel and AMD are using 90 nanometers for their CPU chips and Intel has started using a 65 nanometer process.
• Copper interconnects where copper wiring replaces aluminum for interconnects.
• Low-K dialectric insulators.
• Silicon on insulator (SOI)
• Strained silicon in a process used by IBM known as Strained silicon directly on insulator (SSDOI)

Packaging

The earliest integrated circuits were packaged in ceramic flat packs, which continued to be used by the military for their reliability and small size for many years. Commercial circuit packaging quickly moved to the dual in-line package (DIP), first in ceramic and later in plastic. In the 1980s pin counts of VLSI circuits exceeded the practical limit for DIP packaging, leading to pin grid array (PGA) and leadless chip carrier (LCC) packages. Surface mount packaging appeared in the early 1980s and became popular in the late 1980s, using finer lead pitch with leads formed as either gull-wing or J-lead, as exemplified by Small-Outline Integrated Circuit. A carrier which occupies an area about 30 - 50% less than an equivalent DIP, with a typical thickness that is 70% less. This package has "gull wing" leads protruding from the two long sides and a lead spacing of 0.050 inches.

Related Topics:
Dual in-line package - 1980 - Pin grid array - Leadless chip carrier - Surface mount - Small-Outline Integrated Circuit

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Small-Outline Integrated Circuit (SOIC) and PLCC packages. In the late 1990s, PQFP and TSOP packages became the most common for high pin count devices, though PGA packages are still often used for high-end microprocessors.

Related Topics:
Small-Outline Integrated Circuit (SOIC) - PLCC - PQFP - TSOP - Microprocessor

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Ball grid array (BGA) packages...

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