Formal verification

In the context of hardware and software systems,

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formal verification is the act of

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proving or disproving the correctness of a system

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with respect to a certain formal specification or property,

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using formal methods.

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System types that are considered in the literature for formal verification

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include finite state machines (FSM),

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labelled transition systems (LTS) and

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their compositions,

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Petri nets, timed automata and hybrid automata,

Related Topics:
Petri net - Timed automata - Hybrid automata

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cryptographic protocols,

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combinatorial circuits,

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digital circuits with internal memory,

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and abstractions of general software components.

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The properties to be verified are often described

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in temporal logics, such as linear temporal logic (LTL) or computational tree logic (CTL).

Related Topics:
Linear temporal logic - Computational tree logic

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Usually formal verification is carried out algorithmically.

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The main approaches to implementing formal verification

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include state space enumeration, symbolic state space enumeration, abstract interpretation,

Related Topics:
State space enumeration - Abstract interpretation

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abstraction refinement, process-algebraic methods,

Related Topics:
Abstraction refinement - Process-algebraic

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and reasoning with the aid of automatic theorem provers such as

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HOL or Isabelle.

Related Topics:
HOL - Isabelle

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