Double data rate

In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal, effectively nearly doubling the data transmission rate without having to deal with the additional problems of timing skew that increasing the number of data lines would introduce. This is also known as double pumped, dual-pumped, and double transition.

Related Topics:
Computing - Computer bus - Clock signal - Timing skew

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This technique has been used for the Front side bus, Ultra-3 SCSI, the AGP bus and DDR SDRAM, amongst others.

Related Topics:
Front side bus - Ultra-3 SCSI - AGP - DDR SDRAM

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For some applications, even double pumping has proven insufficient and quadruple data rate (or quad pumping) has been used; transferring data four times per clock. Intel's Pentium 4 utilizes this technique to achieve an effective 800 MHz (200 MHz x 4), or more recently an effective 1066 MHz (266 MHz x 4). Also, the HyperTransport bus on newer AMD Socket 754 and Socket 939 chips is double-pumped.

Related Topics:
Intel - Pentium 4 - HyperTransport - AMD - Socket 754 - Socket 939

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An alternative to double or quad pumping is to make the link self-clocking. This tactic was chosen by Infiniband and PCI Express.

Related Topics:
Self-clocking - Infiniband - PCI Express

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It is often difficult to know how to refer to the speed of a double-pumped bus. Some people talk about the speed of the clock signal and some people prefer to refer to the number of transfers per second. It is less ambiguous to discuss the raw bandwidth of a bus as this also takes into account the width of the bus: thus DDR SDRAM that runs on a clock signal of 100 MHz, with data transfer the same as SDR SDRAM running at about 200 MHz, is called DDR-200 and PC-1600, referring to the bandwidth. However, this does not take into account the bus protocol overhead or latencies, both of which can reduce the effective bandwidth of a bus to a fraction of the raw bandwidth.

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